Issued Patents 2024
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183397 | Memory circuits and devices, and methods thereof | Tung-Cheng Chang, Perng-Fei Yuh, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee | 2024-12-31 |
| 12176049 | MIM eFuse memory devices and fabrication method thereof | Meng-Sheng Chang, Chia-En Huang | 2024-12-24 |
| 12165704 | Memory device with write pulse trimming | Hiroki Noguchi, Yu-Der Chih | 2024-12-10 |
| 12137570 | Three dimensional memory device | Chia-Ta Yu, Chia-En Huang, Yi-Ching Liu, Sai-Hooi Yeong, Yu-Ming Lin | 2024-11-05 |
| 12137571 | Integrated circuit including three-dimensional memory device | Bo-Feng Young, Yi-Ching Liu, Sai-Hooi Yeong, Yu-Ming Lin | 2024-11-05 |
| 12112163 | Memory interface | Hiroki Noguchi | 2024-10-08 |
| 12114506 | Semiconductor structure and method of fabricating the same | Bo-Feng Young, Sai-Hooi Yeong, Shih-Lien Linus Lu, Chia-En Huang, Yu-Ming Lin | 2024-10-08 |
| 12094558 | Multiple stack high voltage circuit for memory | Perng-Fei Yuh, Meng-Sheng Chang, Tung-Cheng Chang | 2024-09-17 |
| 12087354 | Memory device | Tzu-Hsien Yang, Chia-En Huang, Jonathan Tsung-Yung Chang | 2024-09-10 |
| 12089414 | Memory device and method of forming the same | Bo-Feng Young, Sai-Hooi Yeong, Shih-Lien Linus Lu, Chia-En Huang, Yu-Ming Lin | 2024-09-10 |
| 12089402 | Integrated circuit layout and method | Meng-Sheng Chang, Chien-Ying Chen, Chia-En Huang | 2024-09-10 |
| 12087345 | Balanced negative bitline voltage for a write assist circuit | Jui-Che Tsai, Chia-En Huang, Chia-Cheng Chen | 2024-09-10 |
| 12075614 | MIM memory cell with backside interconnect structures | Meng-Sheng Chang, Chia-En Huang | 2024-08-27 |
| 12068284 | Vertical interconnect structures with integrated circuits | Tzu-Hsien Yang, Hiroki Noguchi, Mahmut Sinangil | 2024-08-20 |
| 12063773 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Chia-En Huang, Wan-Hsueh Cheng, Yao-Jen Yang | 2024-08-13 |
| 12063786 | Compute-in-memory device and method | Chieh Lee, Chia-En Huang, Yi-Ching Liu, Wen-Chang Cheng | 2024-08-13 |
| 12062408 | Switches to reduce routing rails of memory system | Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu | 2024-08-13 |
| 12052859 | Non-volatile memory device with reduced area | Meng-Sheng Chang, Chia-En Huang, Yao-Jen Yang | 2024-07-30 |
| 12048147 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Chia-En Huang, Wan-Hsueh Cheng, Yao-Jen Yang | 2024-07-23 |
| 12026404 | Memory device for scheduling maximum number of memory macros write operations at re-arranged time intervals | Hiroki Noguchi, Shih-Lien Linus Lu, Yu-Der Chih | 2024-07-02 |
| 12027204 | Memory including metal rails with balanced loading | Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu | 2024-07-02 |
| 12027220 | One-time-programmable memory | Hiroki Noguchi | 2024-07-02 |
| 12014768 | DRAM computation circuit and method | Chieh Lee, Chia-En Huang, Yi-Ching Liu, Wen-Chang Cheng | 2024-06-18 |
| 12010833 | Method and structure for reduce OTP cell area and leakage | Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou | 2024-06-11 |
| 12002534 | Memory array word line routing | Meng-Han Lin, Chenchen Jacob Wang, Yi-Ching Liu, Han-Jong Chia, Sai-Hooi Yeong +1 more | 2024-06-04 |