Issued Patents 2024
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176049 | MIM eFuse memory devices and fabrication method thereof | Chia-En Huang, Yih Wang | 2024-12-24 |
| 12165865 | Efuse with fuse walls and method of manufacturing the same | Yao-Jen Yang | 2024-12-10 |
| 12148487 | High-density and high-voltage-tolerable pure core memory cell | Ku-Feng Lin, Perng-Fei Yuh | 2024-11-19 |
| 12112829 | Memory array circuits, memory structures, and methods for fabricating a memory array circuit | Chun-Ying Lee, Chia-En Huang | 2024-10-08 |
| 12094558 | Multiple stack high voltage circuit for memory | Perng-Fei Yuh, Tung-Cheng Chang, Yih Wang | 2024-09-17 |
| 12087378 | Bit selection for power reduction in stacking structure during memory programming | Yoshitaka Yamauchi, Perng-Fei Yuh | 2024-09-10 |
| 12089402 | Integrated circuit layout and method | Chien-Ying Chen, Chia-En Huang, Yih Wang | 2024-09-10 |
| 12080641 | Electrical fuse bit cell in integrated circuit having backside conducting lines | Chien-Ying Chen, Yen-Jen Chen, Yao-Jen Yang, Chia-En Huang | 2024-09-03 |
| 12075614 | MIM memory cell with backside interconnect structures | Chia-En Huang, Yih Wang | 2024-08-27 |
| 12073169 | Anti-fuse array | Shao-Yu Chou, Yao-Jen Yang, Chen-Ming Hung | 2024-08-27 |
| 12063773 | Layout structure including anti-fuse cell | Chia-En Huang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2024-08-13 |
| 12062408 | Switches to reduce routing rails of memory system | Chia-En Huang, Yi-Ching Liu, Yih Wang | 2024-08-13 |
| 12052859 | Non-volatile memory device with reduced area | Chia-En Huang, Yao-Jen Yang, Yih Wang | 2024-07-30 |
| 12051464 | Semiconductor memory devices with different word lines | Chia-En Huang, Gu-Huan Li | 2024-07-30 |
| 12048147 | Layout structure including anti-fuse cell | Chia-En Huang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2024-07-23 |
| 12027204 | Memory including metal rails with balanced loading | Chia-En Huang, Yi-Ching Liu, Yih Wang | 2024-07-02 |
| 12027221 | Integrated circuit device | Yao-Jen Yang | 2024-07-02 |
| 12014796 | Memory device and method of operating the same | Ku-Feng Lin | 2024-06-18 |
| 12010833 | Method and structure for reduce OTP cell area and leakage | Chia-En Huang, Shao-Yu Chou, Yih Wang | 2024-06-11 |
| 12002802 | Capacitor and method for forming the same | Meng-Han Lin | 2024-06-04 |
| 11990183 | Memory system with physical unclonable function | — | 2024-05-21 |
| 11985819 | Layout method by buried rail for centralized anti-fuse read current | Chia-En Huang | 2024-05-14 |
| 11978509 | Semiconductor memory devices with differential threshold voltages | Chia-En Huang, Yih Wang | 2024-05-07 |
| 11963348 | Integrated circuit read only memory (ROM) structure | Geng-Cing Lin, Ze-Sian Lu, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen | 2024-04-16 |
| 11955201 | Memory device | Chia-En Huang, Yi-Ching Liu, Yih Wang | 2024-04-09 |