Issued Patents 2024
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183397 | Memory circuits and devices, and methods thereof | Yih Wang, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee | 2024-12-31 |
| 12148487 | High-density and high-voltage-tolerable pure core memory cell | Ku-Feng Lin, Meng-Sheng Chang | 2024-11-19 |
| 12094558 | Multiple stack high voltage circuit for memory | Meng-Sheng Chang, Tung-Cheng Chang, Yih Wang | 2024-09-17 |
| 12087378 | Bit selection for power reduction in stacking structure during memory programming | Meng-Sheng Chang, Yoshitaka Yamauchi | 2024-09-10 |
| 12027583 | Gate structures for semiconductor devices | Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang | 2024-07-02 |
| 12002528 | Memory device and operating method of the same | Gu-Huan Li, Tung-Cheng Chang, Chia-En Huang, Chun-Ying Lee, Yih Wang | 2024-06-04 |
| 11984164 | Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells | Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Hiroki Noguchi, Fu-An Wu | 2024-05-14 |
| 11963463 | MRAM cell and MRAM | Yih Wang | 2024-04-16 |
| 11961706 | Grid structures of ion beam etching (IBE) systems | Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang | 2024-04-16 |
| 11955191 | Semiconductor memory devices with diode-connected MOS | Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang | 2024-04-09 |
| 11955190 | Merged bit lines for high density memory array | — | 2024-04-09 |
| 11953927 | Bias generating devices and methods for generating bias | Yoshitaka Yamauchi, Yih Wang | 2024-04-09 |
| 11903188 | Memory devices, semiconductor devices, and methods of operating a memory device | Yih Wang, Meng-Sheng Chang, Jui-Che Tsai, Ku-Feng Lin, Yu-Wei Lin +7 more | 2024-02-13 |
| 11881242 | Ferroelectric field-effect transistor (FeFET) memory | — | 2024-01-23 |
| 11869954 | Nanostructured channel regions for semiconductor devices | Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang | 2024-01-09 |