GS

Georg Seidemann

IN Intel: 5 patents #385 of 4,430Top 9%
📍 Landshut, DE: #2 of 39 inventorsTop 6%
Overall (2024): #35,511 of 561,600Top 7%
5
Patents 2024

Issued Patents 2024

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
12125815 Assembly of 2XD module using high density interconnect bridges Bernd Waidhas, Andreas Wolter, Thomas Wagner 2024-10-22
12080655 Method to implement wafer-level chip-scale packages with grounded conformal shield Gianni SIGNORINI, Bernd Waidhas 2024-09-03
12057411 Stress relief die implementation Stephan Stoeckl, Wolfgang Molzer, Bernd Waidhas 2024-08-06
11955462 Package stacking using chip to wafer bonding Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes +1 more 2024-04-09
11877403 Printed wiring-board islands for connecting chip packages and methods of assembling same Sonja Koller, Bernd Waidhas 2024-01-16