Issued Patents 2023
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854786 | Deep lines and shallow lines in signal conducting paths | Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu | 2023-12-26 |
| 11842994 | Semiconductor device having staggered gate-stub-size profile and method of manufacturing same | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-12-12 |
| 11810959 | Transistor layout to reduce kink effect | Meng-Han Lin, Wei-Cheng Wu | 2023-11-07 |
| 11737254 | Memory device and layout, manufacturing method of the same | Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-An Lai | 2023-08-22 |
| 11721576 | Semiconductor devices and methods of manufacturing thereof | Shih-Wei Peng, Wei-An Lai, Jiann-Tyng Tzeng | 2023-08-08 |
| 11706914 | Method of forming an array boundary structure to reduce dishing | Meng-Han Lin, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang | 2023-07-18 |
| 11688784 | Transistor layout to reduce kink effect | Meng-Han Lin, Wei-Cheng Wu | 2023-06-27 |
| 11675952 | Integrated circuit, system and method of forming the same | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-06-13 |
| 11646314 | Semiconductor device and manufacture thereof | Shih-Wei Peng, Meng-Hung Shen, Jiann-Tyng Tzeng | 2023-05-09 |
| 11631682 | Metal isolation testing in the context of memory cells | Meng-Han Lin, Wei-Cheng Wu | 2023-04-18 |
| 11626369 | Integrated circuit, system and method of forming same | Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2023-04-11 |
| 11569251 | High voltage polysilicon gate in high-K metal gate device | Meng-Han Lin | 2023-01-31 |
| 11569166 | Semiconductor device and manufacturing method thereof | Wei-An Lai, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng, Kam-Tou Sio | 2023-01-31 |
| 11545491 | Fin field-effect transistor and method of forming the same | Kam-Tou Sio, Jiann-Tyng Tzeng | 2023-01-03 |