Issued Patents 2023
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854974 | Advanced node interconnect routing methodology | Jiann-Tyng Tzeng | 2023-12-26 |
| 11854786 | Deep lines and shallow lines in signal conducting paths | Wei-An Lai, Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu | 2023-12-26 |
| 11842994 | Semiconductor device having staggered gate-stub-size profile and method of manufacturing same | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2023-12-12 |
| 11842967 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2023-12-12 |
| 11842137 | Integrated circuit and method of manufacturing same | Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Shun Li Chen +1 more | 2023-12-12 |
| 11817392 | Integrated circuit | Chia-Tien Wu, Jiann-Tyng Tzeng | 2023-11-14 |
| 11810949 | Semiconductor arrangement and method of making | Jiann-Tyng Tzeng | 2023-11-07 |
| 11797745 | Semiconductor device with reduced power and method of manufacturing the same | Ching-Yu Huang, Jiann-Tyng Tzeng | 2023-10-24 |
| 11783109 | IC device manufacturing method | Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang, Jiann-Tyng Tzeng | 2023-10-10 |
| 11784179 | Structure and method of power supply routing in semiconductor device | Jiann-Tyng Tzeng | 2023-10-10 |
| 11769723 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin, Wei-An Lai | 2023-09-26 |
| 11755808 | Mixed poly pitch design solution for power trim | Lipen Yuan, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2023-09-12 |
| 11755812 | Power structure with power pick-up cell connecting to buried power rail | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2023-09-12 |
| 11741288 | Routing-resource-improving method of generating layout diagram, system for same and semiconductor device | Jiann-Tyng Tzeng, Wei-Cheng Lin, Jay Yang | 2023-08-29 |
| 11737254 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Jiann-Tyng Tzeng, Wei-An Lai | 2023-08-22 |
| 11728269 | Semiconductor device, and associated method and system | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2023-08-15 |
| 11721576 | Semiconductor devices and methods of manufacturing thereof | Te-Hsin Chiu, Wei-An Lai, Jiann-Tyng Tzeng | 2023-08-08 |
| 11720737 | Semiconductor structure, device, and method | Jiann-Tyng Tzeng, Wei-Cheng Lin | 2023-08-08 |
| 11715636 | Method of manufacturing a semiconductor device | Chia-Tien Wu, Jiann-Tyng Tzeng | 2023-08-01 |
| 11704464 | Integrated circuit including misaligned isolation portions | Chih-Ming Lai, Jiann-Tyng Tzeng | 2023-07-18 |
| 11675952 | Integrated circuit, system and method of forming the same | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2023-06-13 |
| 11663389 | Circuit layout | Kam-Tou Sio, Jiann-Tyng Tzeng | 2023-05-30 |
| 11664311 | Method and structure to reduce cell width in semiconductor device | Jiann-Tyng Tzeng | 2023-05-30 |
| 11646314 | Semiconductor device and manufacture thereof | Te-Hsin Chiu, Meng-Hung Shen, Jiann-Tyng Tzeng | 2023-05-09 |
| 11637066 | Integrated circuit and method for forming the same | Wei-Cheng Lin, Cheng-Chi Chuang, Jiann-Tyng Tzeng | 2023-04-25 |