| 11837543 |
Frontside-to-backside intermixing architecture for coupling a frontside network to a backside network |
Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha |
2023-12-05 |
| 11831341 |
Data compressor logic circuit |
Shardendu Shekhar, Yew Keong Chong |
2023-11-28 |
| 11688444 |
Wordline driver architecture |
Akash Bangalore Srinivasa, Yew Keong Chong, Sreebin Sreedhar, Balaji Ravikumar, Penaka Phani Goberu +1 more |
2023-06-27 |
| 11676656 |
Memory architecture with DC biasing |
Yew Keong Chong, Rajiv Kumar Sisodia, Sriram Thyagarajan |
2023-06-13 |
| 11670363 |
Multi-tier memory architecture |
Rahul Mathur, Mudit Bhargava |
2023-06-06 |
| 11664086 |
Column redundancy techniques |
Yew Keong Chong, Bikas Maiti, Vivek Nautiyal |
2023-05-30 |
| 11631439 |
Flexible sizing and routing architecture |
Sriram Thyagarajan, Yew Keong Chong, Munish Kumar, Rajiv Kumar Sisodia |
2023-04-18 |
| 11624777 |
Slew-load characterization |
Sriram Thyagarajan, Pratik Ghanshambhai Satasia, Yew Keong Chong, Mouli Rajaram Chollangi |
2023-04-11 |
| 11586445 |
Modular gated multiplier circuitry and multiplication technique |
Shardendu Shekhar, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong |
2023-02-21 |
| 11569219 |
TSV coupled integrated circuits and methods |
Rahul Mathur, Xiaoqing Xu, Mudit Bhargava, Brian Tracy Cline, Saurabh Sinha |
2023-01-31 |
| 11568926 |
Latch circuitry for memory applications |
Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong |
2023-01-31 |
| 11557583 |
Cell architecture |
Sriram Thyagarajan, Yew Keong Chong, Sony |
2023-01-17 |