Issued Patents 2023
Showing 76–84 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11637090 | Method of forming a 3D stacked compute and memory | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2023-04-25 |
| 11616507 | Ferroelectric based latch | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2023-03-28 |
| 11610620 | Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-03-21 |
| 11611345 | NAND based sequential circuit with ferroelectric or paraelectric material | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2023-03-21 |
| 11610619 | Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-03-21 |
| 11605413 | Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-03-14 |
| 11605411 | Method of forming stacked ferroelectric planar capacitors in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2023-03-14 |
| 11545979 | Compare logic based sequential circuit with ferroelectric or paraelectric material | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2023-01-03 |
| 11545204 | Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2023-01-03 |