Issued Patents 2021
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211327 | Via sizing for IR drop reduction | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2021-12-28 |
| 11205032 | Integrated circuit design method, system and computer program product | Chin-Shen Lin, Kuo-Nan Yang, Hiranmay Biswas | 2021-12-21 |
| 11182527 | Cell placement site optimization | Yen-Hung Lin, Yuan-Te Hou | 2021-11-23 |
| 11176305 | Method and system for sigma-based timing optimization | Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu | 2021-11-16 |
| 11176303 | Constrained cell placement | Yen-Hung Lin, Yuan-Te Hou | 2021-11-16 |
| 11157677 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Kuo-Nan Yang, Yi-Kan Cheng | 2021-10-26 |
| 11113443 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Yung-Chin Hou | 2021-09-07 |
| 11087063 | Method of generating layout diagram including dummy pattern conversion and system of generating same | Ritesh Kumar, Kuo-Nan Yang, Hiranmay Biswas, Shu-Yi Ying | 2021-08-10 |
| 11068637 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao | 2021-07-20 |
| 11068638 | Power grid, IC and method for placing power grid | Hiranmay Biswas, Kuo-Nan Yang | 2021-07-20 |
| 11055466 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Yuan-Te Hou | 2021-07-06 |
| 11030381 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou | 2021-06-08 |
| 11017146 | Integrated circuit and method of forming the same | John Lin, Chin-Shen Lin, Kuo-Nan Yang | 2021-05-25 |
| 11003820 | Method of determining a worst case in timing analysis | Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh | 2021-05-11 |
| 10997347 | Integrated circuit design method, system and computer program product | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang | 2021-05-04 |
| 10990741 | Multiple patterning method and system for implementing the method | Yen-Hung Lin, Yuan-Te Hou | 2021-04-27 |
| 10977415 | Integrated device and method of forming the same | Hiranmay Biswas, Kuo-Nan Yang, Meng-Xiang Lee | 2021-04-13 |
| 10977402 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Sung-Yen Yeh, Li-Chung Hsu | 2021-04-13 |
| 10964685 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2021-03-30 |
| 10956643 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Yuan-Te Hou | 2021-03-23 |
| 10956647 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2021-03-23 |
| 10943045 | Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2021-03-09 |
| 10936785 | Inter-cell leakage-reducing method of generating layout diagram and system for same | Hiranmay Biswas, Kuo-Nan Yang, Jia Han LIN | 2021-03-02 |
| 10922470 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Hiranmay Biswas | 2021-02-16 |