Issued Patents 2021
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211327 | Via sizing for IR drop reduction | Chin-Shen Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2021-12-28 |
| 11205032 | Integrated circuit design method, system and computer program product | Chin-Shen Lin, Chung-Hsing Wang, Kuo-Nan Yang | 2021-12-21 |
| 11157677 | Merged pillar structures and method of generating layout diagram of same | Chung-Hsing Wang, Kuo-Nan Yang, Yi-Kan Cheng | 2021-10-26 |
| 11087063 | Method of generating layout diagram including dummy pattern conversion and system of generating same | Ritesh Kumar, Chung-Hsing Wang, Kuo-Nan Yang, Shu-Yi Ying | 2021-08-10 |
| 11068638 | Power grid, IC and method for placing power grid | Kuo-Nan Yang, Chung-Hsing Wang | 2021-07-20 |
| 10977415 | Integrated device and method of forming the same | Kuo-Nan Yang, Chung-Hsing Wang, Meng-Xiang Lee | 2021-04-13 |
| 10964685 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen +3 more | 2021-03-30 |
| 10943045 | Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same | Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang | 2021-03-09 |
| 10936785 | Inter-cell leakage-reducing method of generating layout diagram and system for same | Chung-Hsing Wang, Kuo-Nan Yang, Jia Han LIN | 2021-03-02 |
| 10922470 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang | 2021-02-16 |