Issued Patents 2021
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211492 | Method of manufacturing semiconductor devices having a SiGe epitaxtial layer containing Ga | Cheng-Yi Peng, Chun Hsiung Tsai, Yu-Ming Lin | 2021-12-28 |
| 11167984 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Ken-Ichi Goto, Shau-Lin Shue, Tai-I Yang | 2021-11-09 |
| 11152565 | Memory device and manufacturing method thereof | Yu-Sheng Chen, Da-Ching Chiou, Jau-Yi Wu | 2021-10-19 |
| 11145806 | Magnetic tunnel junction with reduced damage | Harry-Hak-Lay Chuang, Ru-Liang Lee | 2021-10-12 |
| 11145748 | Semiconductor arrangement with substrate isolation | Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang | 2021-10-12 |
| 11127734 | Vertical nanowire transistor for input/output structure | Jean-Pierre Colinge, Ta-Pen Guo | 2021-09-21 |
| 11114540 | Semiconductor device including standard cells with header/footer switch including negative capacitance | Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh | 2021-09-07 |
| 11104573 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Ta-Pen Guo, Chih-Hao Wang | 2021-08-31 |
| 11063128 | Conformal source and drain contacts for multi-gate field effect transistors | Yee-Chia Yeo, Chih-Hao Wang, Ling-Yen Yeh, Yuan-Chen Sun | 2021-07-13 |
| 11043597 | Method for reducing contact resistance in semiconductor structures | Jean-Pierre Colinge | 2021-06-22 |
| 11038052 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo | 2021-06-15 |
| 11011427 | System and method for widening fin widths for small pitch FinFET devices | Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung | 2021-05-18 |
| 10985159 | Method for manufacturing monolithic three-dimensional (3D) integrated circuits | Jean-Pierre Colinge, Ta-Pen Guo | 2021-04-20 |
| 10964691 | Method for manufacturing monolithic three-dimensional (3D) integrated circuits | Jean-Pierre Colinge, Ta-Pen Guo | 2021-03-30 |
| 10943833 | Silicon and silicon germanium nanowire formation | Kuo-Cheng Chiang, Jean-Pierre Colinge | 2021-03-09 |
| 10930769 | Semiconductor device and manufacturing method thereof | Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang | 2021-02-23 |
| 10930795 | Nanowire stack GAA device with inner spacer and methods for producing the same | I-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen | 2021-02-23 |
| 10923595 | Semiconductor device having a SiGe epitaxial layer containing Ga | Cheng-Yi Peng, Chun Hsiung Tsai, Yu-Ming Lin | 2021-02-16 |
| 10923581 | Method for forming semiconductor structure | Gerben Doornbos, Peter Ramvall, Matthias Passlack | 2021-02-16 |