Issued Patents 2021
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205714 | Dummy structure at fin cut | Shi Ning Ju, Chih-Hao Wang | 2021-12-21 |
| 11195936 | Semiconductor structure | Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung | 2021-12-07 |
| 11171238 | FinFET device with high-k metal gate stack | Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu | 2021-11-09 |
| 11171053 | Transistor device and related methods | Lin-Yu Huang, Huan-Chieh Su, Sheng-Tsung Wang, Zhi-Chang Lin, Jia-Chuan You +4 more | 2021-11-09 |
| 11164786 | Power reduction in finFET structures | Chih-Hao Wang, Kuan-Lun Cheng | 2021-11-02 |
| 11164961 | Epitaxial features confined by dielectric fins and spacers | Kuan-Lun Cheng, Chih-Hao Wang | 2021-11-02 |
| 11158637 | Method and structure for FinFET device | Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu | 2021-10-26 |
| 11145748 | Semiconductor arrangement with substrate isolation | Ching-Wei Tsai, Chih-Hao Wang, Carlos H. Diaz | 2021-10-12 |
| 11145553 | Nonplanar device and strain-generating channel dielectric | Ka-Hing Fung, Zhiqiang Wu | 2021-10-12 |
| 11139381 | Semiconductor device with gate-all-around (GAA) FETs having inner insulating spacers | Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2021-10-05 |
| 11133404 | FinFET device including a stem region of a fin element | Jean-Pierre Colinge, Zhiqiang Wu | 2021-09-28 |
| 11121036 | Multi-gate device and related methods | Huan-Chieh Su, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang | 2021-09-14 |
| 11069793 | Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers | Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng | 2021-07-20 |
| 11038052 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz | 2021-06-15 |
| 11024545 | Semiconductor arrangement and method of manufacture | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu | 2021-06-01 |
| 11011427 | System and method for widening fin widths for small pitch FinFET devices | Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz | 2021-05-18 |
| 11004934 | Semiconductor device including a liner layer between a channel and a source/drain epitaxial layer | Ka-Hing Fung, Ying-Keung Leung | 2021-05-11 |
| 11004960 | Semiconductor device and manufacturing method thereof | Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang | 2021-05-11 |
| 11004959 | Semiconductor device structure and method for forming the same | Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi Ning Ju | 2021-05-11 |
| 11004847 | Semiconductor device and fabricating the same | Ting-Hung Hsu | 2021-05-11 |
| 10998238 | Integrated circuits with buried interconnect conductors | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2021-05-04 |
| 10985277 | Method for forming semiconductor device structure | Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang | 2021-04-20 |
| 10971605 | Dummy dielectric fin design for parasitic capacitance reduction | Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng | 2021-04-06 |
| 10950714 | Semiconductor device and manufacturing method thereof | Kuan-Lun Cheng, Chih-Hao Wang, Keng-Chu Lin, Shi Ning Ju | 2021-03-16 |
| 10943925 | Method of forming FinFET channel and structures thereof | Chih-Hao Wang, Ching-Wei Tsai, Jhon Jhy Liaw, Wai-Yi Lien | 2021-03-09 |