Issued Patents 2021
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11200055 | Systems, methods, and apparatuses for matrix add, subtract, and multiply | Robert Valentine, Dan Baum, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +5 more | 2021-12-14 |
| 11188335 | Apparatuses, methods, and systems for hashing instructions | Regev Shemy, Wajdi K. Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich +5 more | 2021-11-30 |
| 11175891 | Systems and methods to perform floating-point addition with selected rounding | Simon Rubanovich, Amit Gradstein, Mrinmay Dutta | 2021-11-16 |
| 11169802 | Systems, apparatuses, and methods for fused multiply add | Robert Valentine, Galina Ryvchin, Piotr Majcher, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall +4 more | 2021-11-09 |
| 11163565 | Systems, methods, and apparatuses for dot production operations | Robert Valentine, Dan Baum, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +5 more | 2021-11-02 |
| 11150979 | Accelerating memory fault resolution by performing fast re-fetching | Stanislav Shwartsman, Jared W. Stark, IV, Lihu Rappoport, Igor Yanover, George Leifman | 2021-10-19 |
| 11093247 | Systems and methods to load a tile register pair | Raanan Sade, Simon Rubanovich, Amit Gradstein, Alexander Heinecke, Robert Valentine +5 more | 2021-08-17 |
| 11086623 | Systems, methods, and apparatuses for tile matrix multiplication and accumulation | Robert Valentine, Mark J. Charney, Bret L. Toll, Rinat Rappoport, Stanislav Shwartsman +7 more | 2021-08-10 |
| 11080048 | Systems, methods, and apparatus for tile configuration | Menachem Adelman, Robert Valentine, Mark J. Charney, Bret L. Toll, Rinat Rappoport +6 more | 2021-08-03 |
| 11068263 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-07-20 |
| 11068262 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-07-20 |
| 11048587 | Apparatus and method for detecting and recovering from data fetch errors | Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Jose A. Vargas, Hisham Shafi +5 more | 2021-06-29 |
| 11036509 | Enabling removal and reconstruction of flag operations in a processor | Tomer Weiner, Amit Gradstein, Simon Rubanovich, Alex Gerber, Itai Ravid | 2021-06-15 |
| 11036504 | Systems and methods for performing 16-bit floating-point vector dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-06-15 |
| 11023235 | Systems and methods to zero a tile register pair | Raanan Sade, Simon Rubanovich, Amit Gradstein, Alexander Heinecke, Robert Valentine +6 more | 2021-06-01 |
| 11016731 | Using Fuzzy-Jbit location of floating-point multiply-accumulate results | Amit Gradstein, Simon Rubanovich | 2021-05-25 |
| 10990397 | Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator | Amit Gradstein, Simon Rubanovich, Sagi Meller, Jose Yallouz, Robert Valentine | 2021-04-27 |
| 10963246 | Systems and methods for performing 16-bit floating-point matrix dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-03-30 |
| 10942738 | Accelerator systems and methods for matrix operations | Amit Gradstein, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas +4 more | 2021-03-09 |
| 10915421 | Technology for dynamically tuning processor features | Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Adi Yoaz +1 more | 2021-02-09 |