Issued Patents 2021
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11200055 | Systems, methods, and apparatuses for matrix add, subtract, and multiply | Robert Valentine, Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall +5 more | 2021-12-14 |
| 11163565 | Systems, methods, and apparatuses for dot production operations | Robert Valentine, Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall +5 more | 2021-11-02 |
| 11157384 | Methods, systems, articles of manufacture and apparatus for code review assistance for dynamically typed languages | Marcos Carranza, Mats Agerstam, Justin E. Gottschlich, Cesar Martinez-Spessot, Maria Ramirez Loaiza +2 more | 2021-10-26 |
| 11126428 | Computer processor for higher precision computations using a mixed-precision decomposition of operations | Gregory Henry | 2021-09-21 |
| 11093247 | Systems and methods to load a tile register pair | Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Robert Valentine +5 more | 2021-08-17 |
| 11080048 | Systems, methods, and apparatus for tile configuration | Menachem Adelman, Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll +6 more | 2021-08-03 |
| 11068263 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman, Zeev Sperber +2 more | 2021-07-20 |
| 11068262 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman, Zeev Sperber +2 more | 2021-07-20 |
| 11036504 | Systems and methods for performing 16-bit floating-point vector dot product instructions | Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman, Zeev Sperber +2 more | 2021-06-15 |
| 11023235 | Systems and methods to zero a tile register pair | Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Robert Valentine +6 more | 2021-06-01 |
| 10990396 | Systems for performing instructions to quickly convert and use tiles as 1D vectors | Bret L. Toll, Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Raanan Sade +2 more | 2021-04-27 |
| 10970076 | Systems and methods for performing instructions specifying ternary tile logic operations | Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes, Bret L. Toll, Dan Baum, Raanan Sade +2 more | 2021-04-06 |
| 10970072 | Systems and methods to transpose vectors on-the-fly while loading from memory | Evangelos Georganas, Christopher J. Hughes, Raanan Sade, Robert Valentine | 2021-04-06 |
| 10963246 | Systems and methods for performing 16-bit floating-point matrix dot product instructions | Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman, Zeev Sperber +2 more | 2021-03-30 |
| 10963256 | Systems and methods for performing instructions to transform matrices into row-interleaved format | Raanan Sade, Robert Valentine, Bret L. Toll, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall +1 more | 2021-03-30 |
| 10956298 | Methods and apparatus to detect memory leaks in computing systems | Mohammad Mejbah Ul Alam, Jason Martin, Justin E. Gottschlich, Shengtian Zhou | 2021-03-23 |
| 10929143 | Method and apparatus for efficient matrix alignment in a systolic array | Mike Espig, Bret L. Toll, Raanan Sade, Bob Valentine, Christopher J. Hughes | 2021-02-23 |
| 10896043 | Systems for performing instructions for fast element unpacking into 2-dimensional registers | Bret L. Toll, Christopher J. Hughes, Ronen Zohar, Michael Espig, Dan Baum +4 more | 2021-01-19 |