SR

Simon Rubanovich

IN Intel: 17 patents #74 of 5,160Top 2%
Overall (2021): #2,597 of 548,734Top 1%
17
Patents 2021

Issued Patents 2021

Patent #TitleCo-InventorsDate
11200055 Systems, methods, and apparatuses for matrix add, subtract, and multiply Robert Valentine, Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall +5 more 2021-12-14
11188335 Apparatuses, methods, and systems for hashing instructions Regev Shemy, Zeev Sperber, Wajdi K. Feghali, Vinodh Gopal, Amit Gradstein +5 more 2021-11-30
11175891 Systems and methods to perform floating-point addition with selected rounding Amit Gradstein, Zeev Sperber, Mrinmay Dutta 2021-11-16
11176278 Efficient rotate adder for implementing cryptographic basic operations Amit Gradstein, Regev Shemy, Onkar P Desai, Jose Yallouz 2021-11-16
11169802 Systems, apparatuses, and methods for fused multiply add Robert Valentine, Galina Ryvchin, Piotr Majcher, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall +4 more 2021-11-09
11163565 Systems, methods, and apparatuses for dot production operations Robert Valentine, Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall +5 more 2021-11-02
11093247 Systems and methods to load a tile register pair Raanan Sade, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +5 more 2021-08-17
11086623 Systems, methods, and apparatuses for tile matrix multiplication and accumulation Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport +7 more 2021-08-10
11068263 Systems and methods for performing instructions to convert to 16-bit floating-point format Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more 2021-07-20
11068262 Systems and methods for performing instructions to convert to 16-bit floating-point format Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more 2021-07-20
11036504 Systems and methods for performing 16-bit floating-point vector dot product instructions Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more 2021-06-15
11036509 Enabling removal and reconstruction of flag operations in a processor Zeev Sperber, Tomer Weiner, Amit Gradstein, Alex Gerber, Itai Ravid 2021-06-15
11023235 Systems and methods to zero a tile register pair Raanan Sade, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +6 more 2021-06-01
11016731 Using Fuzzy-Jbit location of floating-point multiply-accumulate results Amit Gradstein, Zeev Sperber 2021-05-25
10990397 Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator Amit Gradstein, Sagi Meller, Zeev Sperber, Jose Yallouz, Robert Valentine 2021-04-27
10963246 Systems and methods for performing 16-bit floating-point matrix dot product instructions Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more 2021-03-30
10942738 Accelerator systems and methods for matrix operations Zeev Sperber, Amit Gradstein, Igor Yanover, Gavri Berger, Eyal Hadas +4 more 2021-03-09