Issued Patents 2020
Showing 1–25 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879238 | Negative capacitance finFET and method of fabricating thereof | Kuo-Cheng Ching, Kuan-Lun Cheng, Sai-Hooi Yeong, Tzer-Min Shen, Chi-Hsing Hsu | 2020-12-29 |
| 10879351 | Fill fins for semiconductor devices | Kuo-Cheng Ching, Kuan-Lun Cheng | 2020-12-29 |
| 10879118 | Semiconductor device and method of fabricating the same | Jia-Chuan You, Chia-Hao Chang, Wai-Yi Lien, Yu-Ming Lin | 2020-12-29 |
| 10879242 | Method of manufacturing semiconductor device on hybrid substrate | Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng | 2020-12-29 |
| 10872818 | Buried power rail and method forming same | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng | 2020-12-22 |
| 10872891 | Integrated circuits with gate cut features | Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Kuo-Cheng Ching | 2020-12-22 |
| 10872810 | Fin field effect transistor device structure and method for forming the same | Lin-Yu Huang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin | 2020-12-22 |
| 10868014 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng | 2020-12-15 |
| 10868015 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng | 2020-12-15 |
| 10868000 | Semiconductor device structure with epitaxial structure and method for forming the same | Li-Zhen Yu, Tien-Lu Lin, Jia-Chuan You, Chia-Hao Chang, Yu-Ming Lin | 2020-12-15 |
| 10868001 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Chih-Liang Chen, Shi Ning Ju | 2020-12-15 |
| 10867863 | Semiconductor device structure and method for forming the same | Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin +1 more | 2020-12-15 |
| 10867867 | Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby | Kuo-Cheng Chiang, Chung-Wei Hsu, Lung-Kun Chu, Jia-Ni Yu, Mao-Lin Huang | 2020-12-15 |
| 10861968 | Semiconductor device with negative capacitance structure and method for forming the same | Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui | 2020-12-08 |
| 10861973 | Negative capacitance transistor with a diffusion blocking layer | Chi-Hsing Hsu, Ching-Wei Tsai, Kuan-Lun Cheng, Sai-Hooi Yeong | 2020-12-08 |
| 10861952 | Methods of manufacturing gate-all-around (GAA) FETs through partial replacement of gate spacers | Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng | 2020-12-08 |
| 10854723 | Semiconductor device and method of forming vertical structure | Wai-Yi Lien, Shi Ning Ju, Kai-Chieh Yang, Wen-Ting Lan | 2020-12-01 |
| 10847513 | Buried interconnect conductor | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng | 2020-11-24 |
| 10847373 | Methods of forming silicide contact in field-effect transistors | Chun-Hsiung Lin, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang | 2020-11-24 |
| 10847426 | FinFET devices and methods of forming the same | Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang | 2020-11-24 |
| 10840342 | Methods of forming source/drain contacts in field-effect transistors | Sheng-Tsung Wang, Chia-Hao Chang, Yu-Ming Lin | 2020-11-17 |
| 10833167 | Fin field effect transistor (finFET) device structure and method for forming the same | Sai-Hooi Yeong, Chi On Chui, Bo-Feng Young, Bo-Yu Lai, Kuan-Lun Cheng | 2020-11-10 |
| 10833003 | Integrated circuits with backside power rails | Chih-Chao Chou, Kuo-Cheng Ching, Shi Ning Ju, Wen-Ting Lan | 2020-11-10 |
| 10825918 | Semiconductor device structure and method for forming the same | Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Shi Ning Ju | 2020-11-03 |
| 10825919 | Methods of fabricating semiconductor devices having gate-all-around structure with inner spacer last process | Chun-Hsiung Lin, Pei-Hsun Wang, Kuo-Cheng Ching, Jui-Chien Huang | 2020-11-03 |