CJ

Christian Jacobi

IBM: 57 patents #32 of 11,274Top 1%
📍 West Park, NY: #1 of 1 inventorsTop 100%
🗺 New York: #15 of 13,306 inventorsTop 1%
Overall (2020): #246 of 565,922Top 1%
57
Patents 2020

Issued Patents 2020

Showing 1–25 of 57 patents

Patent #TitleCo-InventorsDate
10831664 Cache structure using a logical directory Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai 2020-11-10
10831502 Migration of partially completed instructions Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy J. Slegel, Aditya N. Puranik +3 more 2020-11-10
10831503 Saving and restoring machine state between multiple executions of an instruction Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy J. Slegel, Aditya N. Puranik +3 more 2020-11-10
10831497 Compression/decompression instruction specifying a history buffer to be used in the compression/decompression of data Bruce C. Giamei, Anthony T. Sofia, Matthias Klein, Simon Weishaupt, Mark S. Farrell +2 more 2020-11-10
10831674 Translation support for a virtual cache Markus Helms, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito +1 more 2020-11-10
10831478 Sort and merge instruction for a general-purpose processor Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy J. Slegel, Aditya N. Puranik +3 more 2020-11-10
10831476 Compare and delay instructions Charles W. Gainey, Jr., Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel 2020-11-10
10824426 Generating and verifying hardware instruction traces including memory data contents Jane H. Bartik, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin 2020-11-03
10824508 High efficiency redundant array of independent memory Patrick J. Meaney, Barry M. Trager 2020-11-03
10810134 Sharing virtual and real translations in a virtual cache Markus Helms, Martin Recktenwald, Johannes C. Reichart 2020-10-20
10802986 Marking to indicate memory used to back address translation structures Jonathan D. Bradbury, Lisa C. Heller, Damian L. Osisek, Anthony Saporito 2020-10-13
10795824 Speculative data return concurrent to an exclusive invalidate request Deanna Postles Dunn Berger, Robert J. Sonnelitter, III, Craig R. Walters 2020-10-06
10740240 Method and arrangement for saving cache power Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter 2020-08-11
10740248 Methods and systems for predicting virtual address David Campbell, Dwain A. Hicks 2020-08-11
10733199 Optimizing data conversion using pattern frequency Markus Helms, Aditya N. Puranik, Parminder Singh 2020-08-04
10732858 Loading and storing controls regulating the operation of a guarded storage facility Dan F. Greiner, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel 2020-08-04
10725685 Load logical and shift guarded instruction Dan F. Greiner, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel 2020-07-28
10725738 Adaptive sort accelerator sharing first level processor cache Aditya N. Puranik, Martin Recktenwald, Christian Zoellin 2020-07-28
10719294 Hardware sort accelerator sharing first level processor cache Aditya N. Puranik, Martin Recktenwald, Christian Zoellin 2020-07-21
10719415 Randomized testing within transactional execution Dan F. Greiner, Timothy J. Slegel 2020-07-21
10713168 Cache structure using a logical directory Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai 2020-07-14
10713048 Conditional branch to an indirectly specified location Dan F. Greiner, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel 2020-07-14
10698836 Translation support for a virtual cache Markus Helms, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito +1 more 2020-06-30
10691412 Parallel sort accelerator sharing first level processor cache Aditya N. Puranik, Martin Recktenwald, Christian Zoellin 2020-06-23
10691604 Minimizing cache latencies using set predictors Dwifuzi Coe, Markus Kaltenbach, Eyal Naor, Martin Recktenwald 2020-06-23