Issued Patents 2020
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10838733 | Register context restoration based on rename register recovery | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2020-11-17 |
| 10782979 | Restoring saved architected registers and suppressing verification of registers to be restored | Michael K. Gschwind, Timothy J. Slegel | 2020-09-22 |
| 10769068 | Concurrent modification of shared cache line by multiple processors | Nicholas C. Matsakis, Craig R. Walters, Jane H. Bartik, Elpida Tzortzatos | 2020-09-08 |
| 10733091 | Read and write sets for ranges of instructions of transactions | Michael K. Gschwind, Valentina Salapura | 2020-08-04 |
| 10725900 | Read and write sets for ranges of instructions of transactions | Michael K. Gschwind, Valentina Salapura | 2020-07-28 |
| 10713048 | Conditional branch to an indirectly specified location | Dan F. Greiner, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2020-07-14 |
| 10671532 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2020-06-02 |
| 10657059 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi | 2020-05-19 |
| 10649785 | Tracking changes to memory via check and recovery | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2020-05-12 |
| 10635592 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi | 2020-04-28 |
| 10621090 | Facility for extending exclusive hold of a cache line in private cache | Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt | 2020-04-14 |
| 10606638 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2020-03-31 |
| 10599567 | Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data | Jane H. Bartik, Nicholas C. Matsakis, Craig R. Walters | 2020-03-24 |
| 10585800 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2020-03-10 |
| 10585697 | Dynamic prediction of hardware transaction resource requirements | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2020-03-10 |
| 10579525 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2020-03-03 |
| 10579377 | Guarded storage event handling during transactional execution | Dan F. Greiner, Christian Jacobi, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel | 2020-03-03 |
| 10572254 | Instruction to query cache residency | Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2020-02-25 |
| 10572298 | Dynamic prediction of hardware transaction resource requirements | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2020-02-25 |
| 10572265 | Selecting register restoration or register reloading | Michael K. Gschwind, Timothy J. Slegel | 2020-02-25 |
| 10565003 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2020-02-18 |
| 10565117 | Instruction to cancel outstanding cache prefetches | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2020-02-18 |
| 10564977 | Selective register allocation | Michael K. Gschwind, Timothy J. Slegel | 2020-02-18 |
| 10558560 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2020-02-11 |
| 10558552 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Christian Jacobi | 2020-02-11 |