Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510953 | Top electrode for device structures in interconnect | Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-12-17 |
| 10510587 | Method for manufacturing semiconductor device | Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Jieh-Jang Chen, Ching-Sen Kuo | 2019-12-17 |
| 10483322 | Memory device and method for fabricating the same | Ching-Pei Hsieh, Yu-Wen Liao | 2019-11-19 |
| 10475852 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao | 2019-11-12 |
| 10388868 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You +2 more | 2019-08-20 |
| 10311952 | Method and apparatus for reading RRAM cell | Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Jen-Sheng Yang, Kuo-Chi Tu +4 more | 2019-06-04 |
| 10276790 | Top electrode for device structures in interconnect | Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-04-30 |
| 10276485 | Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory | Wen-Ting Chu, Yu-Wen Liao | 2019-04-30 |
| 10199575 | RRAM cell structure with laterally offset BEVA/TEVA | Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Chin-Chieh Yang +2 more | 2019-02-05 |
| 10176866 | Recap layer scheme to enhance RRAM performance | Hai-Dang Trinh, Hsing-Lien Lin | 2019-01-08 |