Issued Patents 2019
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10516106 | Electrode structure to improve RRAM performance | Tong-Chern Ong, Ying-Lang Wang | 2019-12-24 |
| 10510953 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-12-17 |
| 10505107 | Switching layer scheme to enhance RRAM performance | Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin | 2019-12-10 |
| 10504963 | RRAM memory cell with multiple filaments | Chin-Chieh Yang, Chih-Yang Chang, Yu-Wen Liao | 2019-12-10 |
| 10497436 | Memory device and fabrication thereof | Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su | 2019-12-03 |
| 10475999 | Metal landing on top electrode of RRAM | Chih-Yang Chang | 2019-11-12 |
| 10475852 | Resistive switching random access memory with asymmetric source and drain | Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Yu-Wen Liao | 2019-11-12 |
| 10388868 | Resistance variable memory structure and method of forming the same | Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih +2 more | 2019-08-20 |
| 10388865 | High yield RRAM cell with optimized film scheme | Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao +1 more | 2019-08-20 |
| 10311952 | Method and apparatus for reading RRAM cell | Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang +4 more | 2019-06-04 |
| 10276790 | Top electrode for device structures in interconnect | Hsia-Wei Chen, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao +2 more | 2019-04-30 |
| 10276489 | Series MIM structures | Kuo-Chi Tu, Chin-Chieh Yang | 2019-04-30 |
| 10276485 | Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory | Hsia-Wei Chen, Yu-Wen Liao | 2019-04-30 |
| 10262731 | Device and method for forming resistive random access memory cell | Chih-Yang Chang, Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang | 2019-04-16 |
| 10249756 | Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof | Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong | 2019-04-02 |
| 10199575 | RRAM cell structure with laterally offset BEVA/TEVA | Chih-Yang Chang, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang +2 more | 2019-02-05 |