Issued Patents 2019
Showing 25 most recent of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521262 | Memory access request for a memory protocol | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Timothy J. Slegel | 2019-12-31 |
| 10521350 | Determining the effectiveness of prefetch instructions | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2019-12-31 |
| 10514913 | Compiler controls for program regions | Valentina Salapura | 2019-12-24 |
| 10515020 | Marking storage keys to indicate memory used to back address translation structures | Jonathan D. Bradbury | 2019-12-24 |
| 10503538 | Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed | Valentina Salapura | 2019-12-10 |
| 10496462 | Providing instructions to facilitate detection of corrupt stacks | Ronald I. McIntosh | 2019-12-03 |
| 10496437 | Context switch by changing memory pointers | Valentina Salapura | 2019-12-03 |
| 10489129 | Layered vector architecture compatibility for cross-system portability | Ronald I. McIntosh | 2019-11-26 |
| 10489382 | Register restoration invalidation based on a context switch | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2019-11-26 |
| 10481909 | Predicted null updates | Valentina Salapura | 2019-11-19 |
| 10481902 | Initialization status of a register employed as a pointer | — | 2019-11-19 |
| 10481908 | Predicted null updated | Valentina Salapura | 2019-11-19 |
| 10474576 | Prefetch protocol for transactional memory | Valentina Salapura, Chung-Lung K. Shum | 2019-11-12 |
| 10474467 | Processor instruction sequence translation | Giles R. Frazier | 2019-11-12 |
| 10474577 | Prefetch protocol for transactional memory | Valentina Salapura, Chung-Lung K. Shum | 2019-11-12 |
| 10467135 | Multi-section garbage collection | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2019-11-05 |
| 10467009 | Processor instruction sequence translation | Giles R. Frazier | 2019-11-05 |
| 10459700 | Independent vector element order and memory byte order controls | William J. Schmidt | 2019-10-29 |
| 10452395 | Instruction to query cache residency | Dan F. Greiner, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2019-10-22 |
| 10445248 | Host page management using active guest page table indicators | Jonathan D. Bradbury, Lisa C. Heller, Christian Jacobi, Damian L. Osisek, Anthony Saporito | 2019-10-15 |
| 10445249 | Facilitating access to memory locality domain information | Jonathan D. Bradbury | 2019-10-15 |
| 10430168 | Context information based on type of routine being called | — | 2019-10-01 |
| 10423412 | Instructions to count contiguous register elements having a specific value in a selected location | Markus Kaltenbach, Jentje Leenstra, Brett Olsson | 2019-09-24 |
| 10394569 | Exception handling for applications with prefix instructions | — | 2019-08-27 |
| 10394568 | Exception handling for applications with prefix instructions | — | 2019-08-27 |