TS

Timothy J. Slegel

IBM: 42 patents #56 of 11,143Top 1%
📍 Staatsburg, NY: #1 of 10 inventorsTop 10%
🗺 New York: #31 of 13,137 inventorsTop 1%
Overall (2019): #436 of 560,194Top 1%
42
Patents 2019

Issued Patents 2019

Showing 1–25 of 42 patents

Patent #TitleCo-InventorsDate
10521350 Determining the effectiveness of prefetch instructions Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum 2019-12-31
10521262 Memory access request for a memory protocol Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura 2019-12-31
10521231 Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor Dan F. Greiner, Lisa C. Heller, Damian L. Osisek 2019-12-31
10496311 Run-time instrumentation of guarded storage event processing Dan F. Greiner, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum 2019-12-03
10496292 Saving/restoring guarded storage controls in a virtualized environment Dan F. Greiner, Christian Jacobi, Damian L. Osisek, Anthony Saporito, Chung-Lung K. Shum 2019-12-03
10489382 Register restoration invalidation based on a context switch Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2019-11-26
10452395 Instruction to query cache residency Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum 2019-10-22
10452288 Identifying processor attributes based on detecting a guarded storage event Dan F. Greiner, Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito 2019-10-22
10437602 Program interruption filtering in transactional execution Dan F. Greiner, Christian Jacobi, Marcel Mitran 2019-10-08
10430199 Program interruption filtering in transactional execution Dan F. Greiner, Christian Jacobi, Marcel Mitran 2019-10-01
10423539 Dynamic address translation with access control in an emulator environment Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more 2019-09-24
10423191 Clock comparator sign control Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Joachim von Buttlar 2019-09-24
10387323 Extract target cache attribute facility and instruction therefor Dan F. Greiner 2019-08-20
10387311 Cache directory that determines current state of a translation in a microprocessor core cache Ute Gaertner, Christian Jacobi, Gregory Miaskovsky, Martin Recktenwald, Aaron Tsai 2019-08-20
10365929 Spin loop delay instruction Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Eric M. Schwarz 2019-07-30
10360033 Conditional transaction end instruction Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt 2019-07-23
10353759 Facilitating transaction completion subsequent to repeated aborts of the transaction Brenton F. Belmar, Christian Jacobi, Randall W. Philley 2019-07-16
10353734 Prioritization of transactions based on execution by transactional core with super core indicator Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz 2019-07-16
10346134 Perform sign operation decimal instruction Jonathan D. Bradbury, Reid T. Copeland, Silvia M. Mueller 2019-07-09
10346305 Interprocessor memory status communication Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum 2019-07-09
10348506 Determination of state of padding operation Dan F. Greiner, Christian Zoellin 2019-07-09
10324728 Lightweight interrupts for condition checking Giles R. Frazier, Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum, Joran S. C. Siu +1 more 2019-06-18
10303569 Simplified processor sparing Gregory W. Alexander, Brian D. Barrick, Shimon Ben-Yehuda, Ophir Erez, Anthony Saporito 2019-05-28
10303478 Convert from zoned format to decimal floating point format Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz 2019-05-28
10296344 Convert from zoned format to decimal floating point format Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz 2019-05-21