| 10365927 |
Non-default instruction handling within transaction |
Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum |
2019-07-30 |
| 10346305 |
Interprocessor memory status communication |
Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel |
2019-07-09 |
| 10310855 |
Non-default instruction handling within transaction |
Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum |
2019-06-04 |
| 10275290 |
Transactional lock elision with delayed lock checking |
Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang |
2019-04-30 |
| 10228943 |
Prefetching of discontiguous storage locations in anticipation of transactional execution |
Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more |
2019-03-12 |
| 10223154 |
Hint instruction for managing transactional aborts in transactional memory computing environments |
Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +2 more |
2019-03-05 |
| 10216635 |
Instruction to cancel outstanding cache prefetches |
Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum |
2019-02-26 |
| 10210019 |
Hint instruction for managing transactional aborts in transactional memory computing environments |
Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +2 more |
2019-02-19 |
| 10168961 |
Hardware transaction transient conflict resolution |
Jonathan D. Bradbury, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more |
2019-01-01 |
| 10169092 |
System, method, program, and code generation unit |
Takuya Nakaike |
2019-01-01 |
