Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521262 | Memory access request for a memory protocol | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2019-12-31 |
| 10353734 | Prioritization of transactions based on execution by transactional core with super core indicator | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2019-07-16 |
| 10268588 | Methods of cache preloading on a partition or a context switch | Vijayalakshmi Srinivasan, Jason D. Zebchuk | 2019-04-23 |
| 10255074 | Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt | Vignyan Reddy Kothinti Naresh, Rami Mohammad Al Sheikh | 2019-04-09 |
| 10223278 | Selective bypassing of allocation in a cache | Shivam Priyadarshi, Brandon H. Dwiel, Rami Mohammad Al Sheikh | 2019-03-05 |
| 10223154 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2019-03-05 |
| 10210019 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2019-02-19 |
| 10185668 | Cost-aware cache replacement | Rami Mohammad Al Sheikh, Shivam Priyadarshi | 2019-01-22 |
| 10169240 | Reducing memory access bandwidth based on prediction of memory request size | Brandon H. Dwiel, Shivam Priyadarshi | 2019-01-01 |