Issued Patents 2019
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521231 | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor | Lisa C. Heller, Damian L. Osisek, Timothy J. Slegel | 2019-12-31 |
| 10496311 | Run-time instrumentation of guarded storage event processing | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2019-12-03 |
| 10496292 | Saving/restoring guarded storage controls in a virtualized environment | Christian Jacobi, Damian L. Osisek, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2019-12-03 |
| 10452395 | Instruction to query cache residency | Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2019-10-22 |
| 10452288 | Identifying processor attributes based on detecting a guarded storage event | Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel | 2019-10-22 |
| 10437602 | Program interruption filtering in transactional execution | Christian Jacobi, Marcel Mitran, Timothy J. Slegel | 2019-10-08 |
| 10430199 | Program interruption filtering in transactional execution | Christian Jacobi, Marcel Mitran, Timothy J. Slegel | 2019-10-01 |
| 10423191 | Clock comparator sign control | Eberhard Engler, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar | 2019-09-24 |
| 10423539 | Dynamic address translation with access control in an emulator environment | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel +1 more | 2019-09-24 |
| 10387323 | Extract target cache attribute facility and instruction therefor | Timothy J. Slegel | 2019-08-20 |
| 10360033 | Conditional transaction end instruction | Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2019-07-23 |
| 10360032 | Performing an operation absent host intervention | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III | 2019-07-23 |
| 10346162 | Selective instruction replacement for assembly language programs | John Robert Dravnieks, John R. Ehrman | 2019-07-09 |
| 10348506 | Determination of state of padding operation | Timothy J. Slegel, Christian Zoellin | 2019-07-09 |
| 10318300 | Parsing-enhancement facility | John R. Ehrman | 2019-06-11 |
| 10313109 | Instruction for performing a pseudorandom number seed operation | Bernd Nerz, Tamas Visegrady | 2019-06-04 |
| 10282327 | Test pending external interruption instruction | Mark S. Farrell, Jeffrey P. Kubala, James H. Mulder, Timothy J. Slegel | 2019-05-07 |
| 10241910 | Creating a dynamic address translation with translation exception qualifiers | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer | 2019-03-26 |
| 10235174 | Conditional instruction end operation | Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2019-03-19 |
| 10235138 | Instruction to provide true random numbers | Bernd Nerz, Timothy J. Slegel, Tamas Visegrady, Christian Zoellin | 2019-03-19 |
| 10228943 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2019-03-12 |
| 10223214 | Randomized testing within transactional execution | Christian Jacobi, Timothy J. Slegel | 2019-03-05 |
| 10223283 | Selective purging of PCI I/O address translation buffer | David F. Craddock, Thomas A. Gregg, Damian L. Osisek | 2019-03-05 |
| 10223154 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2019-03-05 |
| 10216518 | Clearing specified blocks of main storage | Anthony F. Coneski, Beth A. Glendening, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos | 2019-02-26 |