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Efficient hardware-based extraction of program instructions for critical paths |
Jayesh Gaur, Pooja Roy, Sreenivas Subramoney, Ronak Singhal |
2019-12-03 |
| 10459858 |
Programmable event driven yield mechanism which may activate other threads |
Per Hammarlund, Xiang Zou, John Shen, Xinmin Tian, Milind B. Girkar +2 more |
2019-10-29 |
| 10452403 |
Mechanism for instruction set based thread execution on a plurality of instruction sequencers |
John Shen, Edward T. Grochowski, Richard Hankins, Gautham Chinya, Bryant Bigbee +9 more |
2019-10-22 |
| 10387797 |
Instruction and logic for nearest neighbor unit |
Tsung-Han Lin, Gokce Keskin, Hsiang-Tsung Kung, She-Hwa Yen |
2019-08-20 |
| 10331582 |
Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time |
Ishwar Bhati, Huichu Liu, Jayesh Gaur, Kunal Kishore Korgaonkar, Sasikanth Manipatruni +3 more |
2019-06-25 |