Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10331582 | Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time | Ishwar Bhati, Jayesh Gaur, Kunal Kishore Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney +3 more | 2019-06-25 |
| 10261923 | Configurable interconnect apparatus and method | Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Ian A. Young, Tanay Karnik | 2019-04-16 |