Issued Patents 2019
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10331582 | Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time | Huichu Liu, Jayesh Gaur, Kunal Kishore Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney +3 more | 2019-06-25 |