Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10496413 | Efficient hardware-based extraction of program instructions for critical paths | Pooja Roy, Sreenivas Subramoney, Hong Wang, Ronak Singhal | 2019-12-03 |
| 10331582 | Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time | Ishwar Bhati, Huichu Liu, Kunal Kishore Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney +3 more | 2019-06-25 |
| 10268600 | System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor | Sreenivas Subramoney, Sanjay Ganapathy | 2019-04-23 |
| 10176099 | Using data pattern to mark cache lines as invalid | Supratik Majumder, Zvika Greenfield, Israel Diamand | 2019-01-08 |