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Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication |
Asit K. Mishra, Deborah T. Marr |
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Mechanism for instruction set based thread execution on a plurality of instruction sequencers |
Hong Wang, John Shen, Richard Hankins, Gautham Chinya, Bryant Bigbee +9 more |
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Method, system, and apparatus for page sizing extension |
Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa |
2019-10-15 |
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Method, system, and apparatus for page sizing extension |
Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa |
2019-10-15 |
| 10423411 |
Data element comparison processors, methods, systems, and instructions |
Asit K. Mishra, Jonathan Pearce, Deborah T. Marr, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more |
2019-09-24 |
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Zeroing a cache line |
Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Stephen H. Gunther, Buford M. Guy +5 more |
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Interruptible and restartable matrix multiplication instructions, processors, methods, and systems |
Asit K. Mishra, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. |
2019-04-30 |
| 10261904 |
Memory sequencing with coherent and non-coherent sub-systems |
Chunhui Zhang, George Z. Chrysos, Ramacharan Sundararaman, Chung-Lun Chan, Federico Ardanaz |
2019-04-16 |
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Performing power management in a multicore processor |
Victor W. Lee, Daehyun Kim, Yuxin Bai, Sheng Li, Naveen Mellempudi +1 more |
2019-03-19 |