Issued Patents 2019
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489063 | Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication | Asit K. Mishra, Edward T. Grochowski | 2019-11-26 |
| 10452551 | Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register | Ganesh Venkatesh, Christopher B. Wilkerson, Seth H. Pugsley | 2019-10-22 |
| 10437562 | Apparatus and method for processing sparse data | Eriko Nurvitadhi, Yu Wang | 2019-10-08 |
| 10423411 | Data element comparison processors, methods, systems, and instructions | Asit K. Mishra, Edward T. Grochowski, Jonathan Pearce, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more | 2019-09-24 |
| 10409613 | Processing devices to perform a key value lookup instruction | Asit K. Mishra, Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall | 2019-09-10 |
| 10387037 | Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies | Ganesh Venkatesh | 2019-08-20 |
| 10372507 | Compute engine architecture to support data-parallel loops with reduction operations | Ganesh Venkatesh | 2019-08-06 |
| 10289752 | Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller | Ganesh Venkatesh, Nicholas P. Carter | 2019-05-14 |
| 10275247 | Apparatuses and methods to accelerate vector multiplication of vector elements having matching indices | Asit K. Mishra | 2019-04-30 |
| 10198264 | Sorting data and merging sorted data in an instruction set architecture | Asit K. Mishra, Jong Soo Park, Nadathur Rajagopalan Satish, Mikhail Smelyanskiy, Michael Anderson +3 more | 2019-02-05 |
| 10180928 | Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributions | Eriko Nurvitadhi | 2019-01-15 |