Issued Patents 2018
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164070 | Self-aligned passivation of active regions | Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai | 2018-12-25 |
| 10164062 | FinFET device having a channel defined in a diamond-like shape semiconductor structure | You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-12-25 |
| 10164023 | FinFETs with strained well regions | Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-12-25 |
| 10163897 | Inter-level connection for multi-layer structures | Yi-Tang Lin, Neng-Kuo Chen | 2018-12-25 |
| 10158015 | FinFETs with strained well regions | Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-12-18 |
| 10128269 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers | Yi-Tang Lin, Chun Hsiung Tsai | 2018-11-13 |
| 10115826 | Semiconductor structure and the manufacturing method thereof | Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-10-30 |
| 10115597 | Self-aligned dual-metal silicide and germanide formation | Chun Hsiung Tsai, Chi-Yuan Shih, Gin-Chen Huang, Li-Chi Yu, Chin-Hsiang Lin +6 more | 2018-10-30 |
| 10109748 | High-mobility multiple-gate transistor with improved on-to-off current ratio | Chih-Hsin Ko | 2018-10-23 |
| 10096710 | Method of forming strained structures of semiconductor devices | Cheng-Hsien Wu, Chih-Hsin Ko | 2018-10-09 |
| 10062601 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers | Yi-Tang Lin, Chun Hsiung Tsai | 2018-08-28 |
| 10050104 | Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same | Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu +3 more | 2018-08-14 |
| 10043908 | Contact structure of semiconductor device | Ling-Yen Yeh, Chi-Yuan Shih, Yen-Yu Chen | 2018-08-07 |
| 10032889 | Self-aligned passivation of active regions | Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai | 2018-07-24 |
| 10026641 | Isolation structure of semiconductor device | Shu-Han Chen, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-07-17 |
| 10020189 | Growing a III-V layer on silicon using aligned nano-scale patterns | Chih-Hsin Ko | 2018-07-10 |
| 9985131 | Source/drain profile for FinFET | Ta-Chun Ma, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-05-29 |
| 9978630 | Curved wafer processing method and apparatus | I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Tung Ying Lee +2 more | 2018-05-22 |
| 9941367 | Wrap-around contact on FinFET | Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin +5 more | 2018-04-10 |
| 9929133 | Semiconductor logic circuits fabricated using multi-layer structures | Yi-Tang Lin | 2018-03-27 |
| 9929272 | Fin structure of FinFET | Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun | 2018-03-27 |
| 9929158 | Systems and methods for integrating different channel materials into a CMOS circuit by using a semiconductor structure having multiple transistor layers | Yi-Tang Lin | 2018-03-27 |
| 9922827 | Method of forming a semiconductor structure | Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu | 2018-03-20 |
| 9899496 | Method of making a finFET device | Sey-Ping Sun, Sung-Li Wang, Chin-Hsiang Lin, Neng-Kuo Chen | 2018-02-20 |
| 9893160 | Methods of forming gate dielectric material | Liang-Gi Yao, Chia-Cheng Chen | 2018-02-13 |