Issued Patents 2018
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10128261 | Cobalt-containing conductive layers for control gate electrodes in a memory structure | Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi +3 more | 2018-11-13 |
| 10115736 | Methods and apparatus for three-dimensional NAND non-volatile memory devices with side source line and mechanical support | Jin Liu, Chun Ge | 2018-10-30 |
| 10115732 | Three dimensional memory device containing discrete silicon nitride charge storage regions | Jixin Yu, Zhenyu Lu, Daxin Mao, Yanli Zhang, Andrey Serov +1 more | 2018-10-30 |
| 10074666 | Three-dimensional memory device with enhanced mechanical stability semiconductor pedestal and method of making thereof | Chun Ge, Yanli Zhang, Fabo Yu, Jixin Yu | 2018-09-11 |
| 10050054 | Three-dimensional memory device having drain select level isolation structure and method of making thereof | Yanli Zhang, Raghuveer S. Makala, Senaka Kanakamedala, Rahul Sharangpani, James Kai | 2018-08-14 |
| 10038006 | Through-memory-level via structures for a three-dimensional memory device | Yoko Furihata, Jixin Yu, Hiroyuki Ogawa, James Kai, Jin Liu | 2018-07-31 |
| 10008570 | Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device | Jixin Yu, Kento KITAMURA, Tong Zhang, Chun Ge, Yanli Zhang +6 more | 2018-06-26 |
| 9985046 | Method of forming a staircase in a semiconductor device using a linear alignment control feature | Zhenyu Lu, Jixin Yu, Koji Miyata, Makoto Yoshida, Hiro Kinoshita +1 more | 2018-05-29 |
| 9972640 | Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof | James Kai, Murshed Chowdhury, Jin Liu | 2018-05-15 |
| 9972641 | Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof | Yanli Zhang, Jin Liu, Raghuveer S. Makala, Murshed Chowdhury | 2018-05-15 |
| 9959932 | Grouping memory cells into sub-blocks for program speed uniformity | Zhengyi Zhang, Yingda Dong, James Kai | 2018-05-01 |
| 9941295 | Method of making a three-dimensional memory device having a heterostructure quantum well channel | Peter Rabkin, Jayavel Pachamuthu, Masaaki Higashitani | 2018-04-10 |
| 9922987 | Three-dimensional memory device containing separately formed drain select transistors and method of making thereof | Yuki Mizutani, James Kai, Fumiaki Toyama, Shigehiro Fujino | 2018-03-20 |
| 9917100 | Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same | Tong Zhang, James Kai, Jin Liu, Yanli Zhang | 2018-03-13 |
| 9887207 | Three dimensional NAND device having dummy memory holes and method of making thereof | Yanli Zhang, Raghuveer S. Makala, Yao-Sheng Lee, Tiger Xu | 2018-02-06 |
| 9876025 | Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices | Peter Rabkin, Jayavel Pachamuthu, Masaaki Higashitani | 2018-01-23 |
| 9870945 | Crystalline layer stack for forming conductive layers in a three-dimensional memory structure | Jayavel Pachamuthu, Matthias Baenninger, Stephen Shi, Henry Chien | 2018-01-16 |
| 9859004 | Three-dimensional NAND non-volatile memory and dram memory devices on a single substrate | — | 2018-01-02 |
| 9859363 | Self-aligned isolation dielectric structures for a three-dimensional memory device | Zhenyu Lu, Kota Funayama, Chun-Ming Wang, Jixin Yu, Chenche Huang +4 more | 2018-01-02 |