Issued Patents 2018
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10115459 | Multiple liner interconnects for three dimensional memory devices and method of making thereof | Katsuo Yamada, Tomoyasu Kakegawa, Jayavel Pachamuthu, Mohan Dunga, Masaaki Higashitani | 2018-10-30 |
| 9953717 | NAND structure with tier select gate transistors | Jagdish Sabde, Jayavel Pachamuthu | 2018-04-24 |
| 9941295 | Method of making a three-dimensional memory device having a heterostructure quantum well channel | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2018-04-10 |
| 9881929 | Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof | Pradhyumna Ravikirthi, Jayavel Pachamuthu, Jagdish Sabde | 2018-01-30 |
| 9876025 | Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices | Jayavel Pachamuthu, Masaaki Higashitani, Johann Alsmeier | 2018-01-23 |