Issued Patents 2018
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10115459 | Multiple liner interconnects for three dimensional memory devices and method of making thereof | Katsuo Yamada, Tomoyasu Kakegawa, Peter Rabkin, Jayavel Pachamuthu, Masaaki Higashitani | 2018-10-30 |
| 10074440 | Erase for partially programmed blocks in non-volatile memory | Biswajit Ray, Changyuan Chen | 2018-09-11 |
| 10008273 | Cell current based bit line voltage | Biswajit Ray, Gerrit Jan Hemink, Bijesh Rajamohanan, Changyuan Chen | 2018-06-26 |
| 9972396 | System and method for programming a memory device with multiple writes without an intervening erase | Himanshu Hemant Naik, Changyuan Chen, Biswajit Ray | 2018-05-15 |
| 9935050 | Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof | Yuki Mizutani, Zhenyu Lu | 2018-04-03 |