Issued Patents 2018
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10126859 | Touch panel | Yasuhiro Sugita, Kenshi Tada, Shinji Yamagishi, Jean Mugiraneza, Koichi Miyachi +3 more | 2018-11-13 |
| 10115632 | Three-dimensional memory device having conductive support structures and method of making thereof | Yohei Masamori | 2018-10-30 |
| 10038006 | Through-memory-level via structures for a three-dimensional memory device | Yoko Furihata, Jixin Yu, James Kai, Jin Liu, Johann Alsmeier | 2018-07-31 |
| 10020363 | Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device | Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu +2 more | 2018-07-10 |
| 10008570 | Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device | Jixin Yu, Kento KITAMURA, Tong Zhang, Chun Ge, Yanli Zhang +6 more | 2018-06-26 |
| 9991280 | Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same | Tadashi Nakamura, Jin Liu, Kazuya Tokunaga, Marika Gunji-Yoneoka, Matthias Baenninger +6 more | 2018-06-05 |
| 9991282 | Three-dimensional memory device having passive devices at a buried source line level and method of making thereof | Satoshi Shimizu, Yasuo Kasagi, Kento KITAMURA | 2018-06-05 |
| 9985098 | Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device | Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Yohei Masamori, Jixin Yu +2 more | 2018-05-29 |
| 9953992 | Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof | James Kai | 2018-04-24 |
| 9941297 | Vertical resistor in 3D memory device with two-tier stack | Masatoshi Nishikawa, Kota Funayama, Toru Miwa | 2018-04-10 |
| 9935124 | Split memory cells with unsplit select gates in a three-dimensional memory device | Masatoshi Nishikawa, Masafumi Miyamoto | 2018-04-03 |
| 9929174 | Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making thereof | Yuki Mizutani, Fumiaki Toyama, Masaaki Higashitani, Fumitaka Amano, Kota Funayama +1 more | 2018-03-27 |
| 9911748 | Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices | Masatoshi Nishikawa, Kiyohiko Sakakibara, Shuji Minagawa | 2018-03-06 |
| 9899399 | 3D NAND device with five-folded memory stack structure configuration | Hiroyuki Tanaka | 2018-02-20 |
| 9887240 | Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches | Seiji Shimabukuro, Teruyuki Mine, Naoki Takeguchi | 2018-02-06 |
| 9876027 | Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereof | Shinsuke Yada | 2018-01-23 |
| 9876031 | Three-dimensional memory device having passive devices at a buried source line level and method of making thereof | Satoshi Shimizu, Yasuo Kasagi, Kento KITAMURA | 2018-01-23 |
| 9870111 | Touchscreen panel with driving electrodes connected to a plurality of lead lines extending in parallel to sensing electrodes | Yasuhiro Sugita, Kenshi Tada, Yuuichi Kanbayashi, Shinji Yamagishi | 2018-01-16 |
| 9870493 | Antenna loop configuration for more efficiently surrounding the high intensity area of the magnetic field produced by an IC card | Yuhji Yashiro, Yasuhiro Sugita | 2018-01-16 |
| 9864457 | Display device with touch sensor | Kenshi Tada, Yasuhiro Sugita, Shinji Yamagishi, Jean Mugiraneza | 2018-01-09 |