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USPTO Patent Rankings Data through Dec 31, 2025
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Brian S. Morris — 9 Patents in 2018

Intel: 9 patents #168 of 5,158Top 4%
Santa Clara, CA: #39 of 1,667 inventorsTop 3%
California: #1,219 of 60,411 inventorsTop 3%
Overall (2018): #8,978 of 503,207Top 2%
9 Patents 2018

Issued Patents 2018

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10163508 Supporting multiple memory types in a memory slot Woojong Han, Mohamed Arafa, Mani N. Prakash, James K. Pickett, John K. Grooms +3 more 2018-12-25
10102886 Techniques for probabilistic dynamic random access memory row repair John H. Crawford, Sreenivas Mandava, Raj K. Ramanujan 2018-10-16 $21,459,000
10061719 Packed write completions Jeffrey C. Swanson, Bill Nale, Robert G. Blankenship, Jeff Willey, Eric L. Hendrickson 2018-08-28 $28,989,000
10042562 Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device Vedaraman Geetha, Henk G. Neefs, Sreenivas Mandava, Massimo Sutera 2018-08-07 $25,284,000
10031861 Protect non-memory encryption engine (non-mee) metadata in trusted execution environment Siddhartha Chhabra, Binata Bhattacharyya, Raghunandan Makaram 2018-07-24 $23,531,000
10007606 Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory Vedaraman Geetha, Binata Bhattacharyya, Massimo Sutera 2018-06-26 $24,418,000
9959418 Supporting configurable security levels for memory address ranges Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson +1 more 2018-05-01 $34,156,000
9934143 Mapping a physical address differently to different memory devices in a group Kuljit S. Bains, Suneeta Sah, John H. Crawford 2018-04-03 $16,515,000
9910728 Method and apparatus for partial cache line sparing Debaleena Das, Rajat Agarwal 2018-03-06 $18,859,000