Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163508 | Supporting multiple memory types in a memory slot | Woojong Han, Mohamed Arafa, Mani N. Prakash, James K. Pickett, John K. Grooms +3 more | 2018-12-25 |
| 10102886 | Techniques for probabilistic dynamic random access memory row repair | John H. Crawford, Sreenivas Mandava, Raj K. Ramanujan | 2018-10-16 |
| 10061719 | Packed write completions | Jeffrey C. Swanson, Bill Nale, Robert G. Blankenship, Jeff Willey, Eric L. Hendrickson | 2018-08-28 |
| 10042562 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Vedaraman Geetha, Henk G. Neefs, Sreenivas Mandava, Massimo Sutera | 2018-08-07 |
| 10031861 | Protect non-memory encryption engine (non-mee) metadata in trusted execution environment | Siddhartha Chhabra, Binata Bhattacharyya, Raghunandan Makaram | 2018-07-24 |
| 10007606 | Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory | Vedaraman Geetha, Binata Bhattacharyya, Massimo Sutera | 2018-06-26 |
| 9959418 | Supporting configurable security levels for memory address ranges | Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson +1 more | 2018-05-01 |
| 9934143 | Mapping a physical address differently to different memory devices in a group | Kuljit S. Bains, Suneeta Sah, John H. Crawford | 2018-04-03 |
| 9910728 | Method and apparatus for partial cache line sparing | Debaleena Das, Rajat Agarwal | 2018-03-06 |