Issued Patents 2018
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140213 | Two level memory full line writes | Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu | 2018-11-27 |
| 10042562 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Henk G. Neefs, Brian S. Morris, Sreenivas Mandava, Massimo Sutera | 2018-08-07 |
| 10007606 | Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory | Brian S. Morris, Binata Bhattacharyya, Massimo Sutera | 2018-06-26 |