Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140213 | Two level memory full line writes | Robert G. Blankenship, Jeffrey D. Chamberlain, Vedaraman Geetha | 2018-11-27 |
| 10078592 | Resolving multi-core shared cache access conflicts | Krishnakanth V. Sistla, Zhong-Ning Cai, Jeffrey D. Gilbert | 2018-09-18 |
| 10031848 | Method and apparatus for improving snooping performance in a multi-core multi-processor | Krishnakanth V. Sistla, Zhong-Ning Cai | 2018-07-24 |
| 9921989 | Method, apparatus and system for modular on-die coherent interconnect for packetized communication | Krishnakumar Ganapathy, Antonio Juan, Steven R. Page, Jeffrey D. Chamberlain, Pau CABRE +2 more | 2018-03-20 |
| 9910807 | Ring protocol for low latency interconnect switch | Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Bahaa Fahim, Ganapati Srinivasa | 2018-03-06 |