Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162750 | System address reconstruction | — | 2018-12-25 |
| 10042562 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Sreenivas Mandava | 2018-08-07 |
| 10007606 | Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory | Vedaraman Geetha, Brian S. Morris, Binata Bhattacharyya | 2018-06-26 |