Issued Patents 2018
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10102126 | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes | Raj K. Ramanujan, Glenn J. Hinton | 2018-10-16 |
| 9910728 | Method and apparatus for partial cache line sparing | Debaleena Das, Brian S. Morris | 2018-03-06 |