Issued Patents 2018
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10107860 | Bitwise rotating scan section for microelectronic chip testing and diagnostics | Todd L. Cohen, Hari Krishnan Rajeev, Timothy C. Taylor | 2018-10-23 |
| 10088524 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2018-10-02 |
| 10067183 | Portion isolation architecture for chip isolation test | Steven M. Douskey, Raghu G. Gaurav, Hari Krishnan Rajeev | 2018-09-04 |
| 10060971 | Adjusting latency in a scan cell | Steven M. Douskey, Raghu G. GopalaKrishnaSetty | 2018-08-28 |
| 10024910 | Iterative N-detect based logic diagnostic technique | Gary W. Maier, Franco Motika, Phong T. Tran | 2018-07-17 |
| 10018672 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2018-07-10 |
| 10018671 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2018-07-10 |
| 10001523 | Adjusting latency in a scan cell | Steven M. Douskey, Raghu G. GopalaKrishnaSetty | 2018-06-19 |
| 9929749 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-27 |
| 9923579 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-20 |
| 9915701 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-13 |
| 9910090 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-06 |