Issued Patents 2018
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10067183 | Portion isolation architecture for chip isolation test | Raghu G. Gaurav, Mary P. Kusko, Hari Krishnan Rajeev | 2018-09-04 |
| 10060978 | Implementing prioritized compressed failure defects for efficient scan diagnostics | Michael J. Hamilton, Amanda R. Kaufer | 2018-08-28 |
| 10060971 | Adjusting latency in a scan cell | Raghu G. GopalaKrishnaSetty, Mary P. Kusko | 2018-08-28 |
| 10024917 | Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through spreading in stumpmux daisy-chain structure | Michael J. Hamilton, Amanda R. Kaufer, Phillip A. Senum | 2018-07-17 |
| 10024914 | Diagnosing failure locations of an integrated circuit with logic built-in self-test | Amanda R. Kaufer, Leah Pfeifer Pastel | 2018-07-17 |
| 10001523 | Adjusting latency in a scan cell | Raghu G. GopalaKrishnaSetty, Mary P. Kusko | 2018-06-19 |
| 9964591 | Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation | Michael J. Hamilton, Amanda R. Kaufer, Phillip A. Senum | 2018-05-08 |