Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9761679 | Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device | Katsunori Onishi, Jian-Shen Yu | 2017-09-12 |
| 9735058 | Method of forming performance optimized gate structures by silicidizing lowered source and drain regions | Katsunori Onishi, Jian-Shen Yu | 2017-08-15 |
| 9722045 | Buffer layer for modulating Vt across devices | Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Claude Ortolland, Judson R. Holt | 2017-08-01 |
| 9639652 | Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors | Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park +2 more | 2017-05-02 |
| 9559284 | Silicided nanowires for nanobridge weak links | Josephine B. Chang, Guy M. Cohen, Michael A. Guillorn | 2017-01-31 |