Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837312 | Atomic layer etching for enhanced bottom-up feature fill | Samantha Tan, Taeseung Kim, Jengyi Yu, Praveen Nalla, Novy Tjokro +1 more | 2017-12-05 |
| 9818617 | Method of electroless plating using a solution with at least two borane containing reducing agents | Praveen Nalla, Xiaomin Bin, Nanhai Li, Yaxin Wang, Patrick William Little +1 more | 2017-11-14 |
| 9778561 | Vacuum-integrated hardmask processes and apparatus | Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie +3 more | 2017-10-03 |
| 9768063 | Dual damascene fill | Praveen Nalla, Lie Zhao | 2017-09-19 |
| 9761524 | Metallization of the wafer edge for optimized electroplating performance on resistive substrates | — | 2017-09-12 |
| 9691622 | Pre-fill wafer cleaning formulation | — | 2017-06-27 |
| 9583386 | Interlevel conductor pre-fill utilizing selective barrier deposition | William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani +2 more | 2017-02-28 |
| 9551074 | Electroless plating solution with at least two borane containing reducing agents | Praveen Nalla, Xiaomin Bin, Nanhai Li, Yaxin Wang, Patrick William Little +1 more | 2017-01-24 |