Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773698 | Method of manufacturing an ultra low dielectric layer | Geraud Jean-Michel Dubois, Gregory M. Fritz, Teddie Peregrino Magbitang, Hiroyuki Miyazoe, Willi Volksen | 2017-09-26 |
| 9653395 | Hybrid subtractive etch/metal fill process for fabricating interconnects | Gregory M. Fritz, Eric A. Joseph, Hiroyuki Miyazoe | 2017-05-16 |
| 9646881 | Hybrid subtractive etch/metal fill process for fabricating interconnects | Gregory M. Fritz, Eric A. Joseph, Hiroyuki Miyazoe | 2017-05-09 |
| 9636675 | Pillar array structure with uniform and high aspect ratio nanometer gaps | Yann Astier, Joshua T. Smith, Chao Wang, Benjamin H. Wunsch | 2017-05-02 |
| 9633948 | Low energy etch process for nitrogen-containing dielectric layer | Markus Brink, Sebastian U. Engelmann, Nicholas C. M. Fuller, Hiroyuki Miyazoe, Masahiro Nakamura | 2017-04-25 |
| 9615851 | Method and apparatus for insertion of a sensor | Mark Neinast, W. Kenneth Ward, Richard G. Sass, Jon A. Fortuna | 2017-04-11 |
| 9536731 | Wet clean process for removing CxHyFz etch residue | Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao +3 more | 2017-01-03 |