| 9852946 |
Self aligned conductive lines |
Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more |
2017-12-26 |
| 9786554 |
Self aligned conductive lines |
Sean D. Burns, Lawrence A. Clevenger, Anuja E. DeSilva, Nelson Felix, Sivananda K. Kanakasabapathy +3 more |
2017-10-10 |
| 9779944 |
Method and structure for cut material selection |
Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy +3 more |
2017-10-03 |
| 9773700 |
Aligning conductive vias with trenches |
Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more |
2017-09-26 |
| 9711507 |
Separate N and P fin etching for reduced CMOS device leakage |
Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve +3 more |
2017-07-18 |
| 9659820 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +2 more |
2017-05-23 |
| 9658523 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +1 more |
2017-05-23 |
| 9607886 |
Self aligned conductive lines with relaxed overlay |
Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more |
2017-03-28 |
