Issued Patents 2017
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9679875 | Reduced volume interconnect for three-dimensional chip stack | Peter A. Gruber, Katsuyuki Sakuma | 2017-06-13 |
| 9679882 | Method of multi-chip wafer level packaging | Chih-Hang Tung, Chun-Hui Yu, Chen-Hua Yu | 2017-06-13 |
| 9543273 | Reduced volume interconnect for three-dimensional chip stack | Peter A. Gruber, Katsuyuki Sakuma | 2017-01-10 |