Issued Patents 2017
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9851978 | Restricted instructions in transactional execution | Dan F. Greiner, Timothy J. Slegel | 2017-12-26 |
| 9836405 | Dynamic management of virtual memory blocks exempted from cache memory access | Jonathan D. Bradbury, Dan F. Greiner, Michael K. Gschwind, Younes Manton, Anthony Saporito +1 more | 2017-12-05 |
| 9817693 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2017-11-14 |
| 9811337 | Transaction abort processing | Dan F. Greiner, Timothy J. Slegel | 2017-11-07 |
| 9792125 | Saving/restoring selected registers in transactional processing | Dan F. Greiner, Timothy J. Slegel | 2017-10-17 |
| 9792124 | Speculative branch handling for transaction abort | Michael Billeci, James J. Bonanno, Adam B. Collura, Anthony Saporito, Timothy J. Slegel | 2017-10-17 |
| 9772854 | Selectively controlling instruction execution in transactional processing | Dan F. Greiner, Robert R. Rogers, Timothy J. Slegel | 2017-09-26 |
| 9766925 | Transactional processing | Dan F. Greiner, Timothy J. Slegel | 2017-09-19 |
| 9760511 | Efficient interruption routing for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +7 more | 2017-09-12 |
| 9740521 | Constrained transaction execution | Dan F. Greiner, Timothy J. Slegel | 2017-08-22 |
| 9740549 | Facilitating transaction completion subsequent to repeated aborts of the transaction | Brenton F. Belmar, Randall W. Philley, Timothy J. Slegel | 2017-08-22 |
| 9727484 | Dynamic cache memory management with translation lookaside buffer protection | Jonathan D. Bradbury, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2017-08-08 |
| 9720764 | Uncorrectable memory errors in pipelined CPUs | Michael Billeci, Uwe Brandt, Martin Recktenwald | 2017-08-01 |
| 9720441 | Generating time-of-day values without causing execution stalls | Eberhard Engler, Martin Recktenwald, Timothy J. Slegel | 2017-08-01 |
| 9716515 | Method for detecting end of record in variable length coded bit stream | Deepankar Bhattacharjee, Jonathan D. Bradbury, Aditya N. Puranik, Christian Zoellin | 2017-07-25 |
| 9715377 | Behavior based code recompilation triggering scheme | Jonathan D. Bradbury, Giles R. Frazier, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2017-07-25 |
| 9710267 | Instruction to compute the distance to a specified memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2017-07-18 |
| 9710266 | Instruction to compute the distance to a specified memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2017-07-18 |
| 9703907 | RAS evaluation for circuit element | Udo Krautz | 2017-07-11 |
| 9697132 | Store forwarding cache | Khary J. Alexander, Jonathan T. Hsieh, James R. Mitchell | 2017-07-04 |
| 9680653 | Cipher message with authentication instruction | Jonathan D. Bradbury, Reinhard T. Buendgen, Dan F. Greiner, Volodymyr Paprotski, Aditya N. Puranik +3 more | 2017-06-13 |
| 9665486 | Hierarchical cache structure and handling thereof | Christian Habermann, Martin Recktenwald, Hans-Werner Tast | 2017-05-30 |
| 9665376 | Sharing program interrupt logic in a multithreaded processor | Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Timothy J. Slegel | 2017-05-30 |
| 9639370 | Software instructed dynamic branch history pattern adjustment | Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2017-05-02 |
| 9626293 | Single-thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Brian R. Prasky +4 more | 2017-04-18 |