Issued Patents 2017
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9619237 | Speculative branch handling for transaction abort | Michael Billeci, James J. Bonanno, Adam B. Collura, Anthony Saporito, Timothy J. Slegel | 2017-04-11 |
| 9619385 | Single thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Brian R. Prasky +4 more | 2017-04-11 |
| 9612963 | Store forwarding cache | Khary J. Alexander, Jonathan T. Hsieh, James R. Mitchell | 2017-04-04 |
| 9594683 | Data processing in a multiple processor system to maintain multiple processor cache memory access coherency | Jens-Peter Dittrich, Matthias Pflanz, Stefan Schuh, Kai Weber | 2017-03-14 |
| 9582413 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-02-28 |
| 9569338 | Fingerprint-initiated trace extraction | Jonathan D. Bradbury, Giles R. Frazier, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2017-02-14 |
| 9569573 | RAS evaluation for circuit element | Udo Krautz | 2017-02-14 |
| 9569370 | Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB) | Khary J. Alexander, Jonathan T. Hsieh, Timothy J. Slegel | 2017-02-14 |
| 9563568 | Hierarchical cache structure and handling thereof | Christian Habermann, Martin Recktenwald, Hans-Werner Tast | 2017-02-07 |
| 9558032 | Conditional instruction end operation | Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2017-01-31 |
| 9552278 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Chung-Lung K. Shum | 2017-01-24 |
| 9547523 | Conditional instruction end operation | Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2017-01-17 |
| 9547484 | Automated compiler operation verification | Giles R. Frazier, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum, Joran S. C. Siu | 2017-01-17 |